Aditya Bansal, Keunwoo Kim, et al.
ICICDT 2007
We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultra-thin body (UTB) fully-depleted SOI (FD-SOI) transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2-D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier. © 2007 IEEE.
Aditya Bansal, Keunwoo Kim, et al.
ICICDT 2007
Meng-Hsueh Chiang, Keunwoo Kim, et al.
IEEE International SOI Conference 2004
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IRPS 2015
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