Fully on-chip MAC at 14nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-formatP. NarayananS. Ambrogioet al.2021VLSI 2021
On-Chip Trainable 1.4M 6T2R PCM Synaptic Array with 1.6K Stochastic LIF Neurons for Spiking RBMMasatoshi IshiiU. Shinet al.2019IEDM 2019
NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learningSangbum KimMasatoshi Ishiiet al.2015IEDM 2015
220 mm2 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architectureT. KirihataM. Gallet al.1998ISSCC 1998
Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)Geoffrey BurrSidney Tsaiet al.2023IEDM 2023
Phase Change Memory-based Hardware Accelerators for Deep Neural NetworksGeoffrey BurrPritish Narayananet al.2023VLSI Technology 2023
Analog In-Memory Computing for Deep Neural Network AccelerationAndrea FasoliGeoffrey Burret al.2023MRS Spring Meeting 2023
Impact of PCM noise on the Spiking Restricted Boltzmann Machine via On-Chip Trainable PCM synapsesUicheol ShinMasatoshi Ishiiet al.2022MRS Fall Meeting 2022
An analog-AI chip for energy-efficient speech recognition and transcriptionS. AmbrogioPritish Narayananet al.2023Nature