22nm technology yield optimization using multivariate 3D virtual fabrication
- B. Cipriany
- B. Jagannathan
- et al.
- 2013
- SISPAD 2013
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24 results for D. Fried
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
- S. Narasimha
- P. Chang
- et al.
- 2012
- IEDM 2012
SOI CMOS technology with 360GHz fT NFET, 260GHz fT PFET, and record circuit performance for millimeter-wave digital and analog system-on-chip applications
- Sungjae Lee
- Jonghae Kim
- et al.
- 2007
- VLSI Technology 2007
A simple hardware-based statistical model on 65nm SOI CMOS technology
- Q. Liang
- J.B. Johnson
- et al.
- 2007
- ISDRS 2007
CMOS fabricated by hybrid-orientation technology (HOT)
- Bin Yang
- M. Yang
- et al.
- 2007
- IEDST 2007
Integration of local stress techniques with strained-Si directly on insulator (SSDOI) substrates
- Haizhou Yin
- Z. Ren
- et al.
- 2006
- VLSI Technology 2006
Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
Hybrid-orientation technology (HOT): Opportunities and challenges
- Min Yang
- Victor W.C. Chan
- et al.
- 2006
- IEEE Transactions on Electron Devices
Hybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes
- Steven Steen
- Sharee J. McNab
- et al.
- 2006
- Microelectronic Engineering
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- W.-H. Lee
- A. Waite
- et al.
- 2005
- IEDM 2005