High performance CMOS variability in the 65nm regime and beyond
- Sani Nassif
- Kerry Bernstein
- et al.
- 2007
- IEDM 2007
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178 results for Wilfried Haensch
Ultra-low leakage silicon-on-insulator technology for 65 nm node and beyond
- Jin Cai
- Amlan Majumdar
- et al.
- 2007
- IEDM 2007
Interconnects in the third dimension: Design challenges for 3D ICs
- Kerry Bernstein
- Paul Andry
- et al.
- 2007
- DAC 2007
Challenges and opportunities for high performance 32 nm CMOS technology
- J. Sleight
- I. Lauer
- et al.
- 2006
- IEDM 2006
Structure, design and process control for Cu bonded interconnects in 3D integrated circuits
- Kuan-Neng Chen
- Sang Hwui Lee
- et al.
- 2006
- IEDM 2006
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
- D. Singh
- J. Sleight
- et al.
- 2005
- IEDM 2005
Selective epitaxial channel ground plane thin SOI CMOS devices
- Zhibin Ren
- M. Ieong
- et al.
- 2005
- IEDM 2005
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- J. Cai
- K. Rim
- et al.
- 2004
- IEDM 2004
Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyond
- D. Fried
- J. Hergenrother
- et al.
- 2004
- IEDM 2004
Device Design Considerations for Ultra-Thin SOI MOSFETs
- B. Doris
- M. Ieong
- et al.
- 2003
- IEDM 2003