A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
- Gary S. Ditlow
- Robert K. Montoye
- et al.
- 2011
- ISSCC 2011
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9 results for Gary Ditlow
Random Pattern Testability
- Jacob Savir
- Gary S. Ditlow
- et al.
- 1984
- IEEE TC
1Mb 0.41 μm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert Montoye
- et al.
- 2013
- VLSI Circuits 2013
1Mb 0.41 μm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
- Jing Li
- Robert Montoye
- et al.
- 2013
- VLSI Technology 2013
Layout-aware through-process circuit analysis
- Rama Singh
- Matt Ziegler
- et al.
- 2007
- DTIS 2007
Structured and tuned array generation (STAG) for high-performance random logic
- Matthew M. Ziegler
- Gary S. Ditlow
- et al.
- 2007
- GLSVLSI 2007
Integrated manufacturing and development (IMaD)
- David Moran
- Daria Dooling
- et al.
- 1999
- ACM/IEEE SC 1999
Algorithms for the design verification of bipolar array chips
- D.A. Zein
- O.P. Engel
- et al.
- 1992
- VTS 1992
Circuit Analysis, Logic Simulation, and Design Verification for VLSI
- Albert E. Ruehli
- Gary S. Ditlow
- 1983
- Proceedings of the IEEE