Matthew M. Ziegler, Victor V. Zyuban, et al.
ISLPED 2009
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides a complete design solution from logic to layout for regularly structured circuits. The STAG circuit tuning constraints are a key component of the methodology. The tuning contraints first guide a SPICE-level tuner to a violation free region in the design space. Secondly, the tuning methodology provides flexibility for targeting a variety of design contraints and objectives. Design examples illustrate STAG's ability for fast turnaround time as well as for high performance and timing critical random logic. Copyright 2007 ACM.
Matthew M. Ziegler, Victor V. Zyuban, et al.
ISLPED 2009
Milos Stanisavljevic, Frank Kagan Gürkaynak, et al.
GLSVLSI 2007
Phillip Chin, Charles A. Zukowski, et al.
Integration, the VLSI Journal
Stephen V. Kosonocky, Azeez J. Bhavnagarwala, et al.
IBM J. Res. Dev