Variable-size shallow trench isolation (STI) technology with diffused sidewall doping for submicron CMOS
- B. Davari
- C. Koburger
- et al.
- 1988
- IEDM 1988
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83 results for Yuan Taur
Doping of n+ and p+ polysilicon in a dual-gate CMOS process
- C.Y. Wong
- J.Y.-C. Sun
- et al.
- 1988
- IEDM 1988
A high performance liquid-nitrogen CMOS SRAM technology
- J.Y.-C. Sun
- S. Klepner
- et al.
- 1988
- ESSDERC 1988
0.5 μm CMOS device design and characterization
- H.I. Hanafi
- M.R. Wordeman
- et al.
- 1987
- ESSDERC 1987
Source-Drain Contact Resistance in CMOS with Self-Aligned TiSi2
- Yuan Taur
- Jack Yuan-Chen Sun
- et al.
- 1987
- IEEE T-ED
Submicrometer-Channel CMOS for Low-Temperature Operation
- Jack Yuan-Chen Sun
- Yuan Taur
- et al.
- 1987
- IEEE T-ED
0. 5 MICRON GATE CMOS TECHNOLOGY USING E-BEAM/OPTICAL MIX LITHOGRAPHY.
- L.K. Wang
- Y. Taur
- et al.
- 1985
- VLSI Technology 1985
0. 5- mu M-CHANNEL CMOS TECHNOLOGY OPTIMIZED FOR LIQUID-NITROGEN-TEMPERATURE OPERATION.
- J.Y.-C. Sun
- Y. Taur
- et al.
- 1985
- IEDM 1985
A Highly Latchup-Immune 1-μm CMOS Technology Fabricated with 1-MeV Ion Implantation and Self-Aligned TiSi2
- Fang-Shi J. Lai
- L.K. Wang
- et al.
- 1986
- IEEE T-ED
HIGHLY LATCHUP-IMMUNE 1- mu m CMOS TECHNOLOGY FABRICATED WITH 1 Mev ION IMPLANTATION AND SELF-ALIGNED TiSi//2.
- F.S. Lai
- L.K. Wang
- et al.
- 1984
- IEDM 1984