Very high performance 50 nm CMOS at low temperature
- S.J. Wind
- L.T. Shi
- et al.
- 1999
- IEDM 1999
Publications
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83 results for Yuan Taur
25 nm CMOS design considerations
- Y. Taur
- C. Wann
- et al.
- 1998
- IEDM 1998
RF perspective of sub-tenth-micron CMOS
- C. Wann
- L. Su
- et al.
- 1998
- ISSCC 1998
Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
- H.-S. Wong
- K.K. Chan
- et al.
- 1997
- IEDM 1997
Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1996
- IEDM 1996
Probing the limits of silicon-based nanoelectronics
- S.J. Wind
- Y. Taur
- et al.
- 1995
- MRS Spring Meeting 1995
Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs
- H.-S. Wong
- D.J. Frank
- et al.
- 1994
- IEDM 1994
Three-Dimensional “Atomistic” Simulation of Discrete Random Dopant Distribution Effects in Sub-0.1μm MOSFET's
- Hon-Sum Wong
- Yuan Taur
- 1993
- IEDM 1993
High Performance 0.1 μm CMOS Devices with 1.5 V Power Supply
- Y. Taur
- S.J. Wind
- et al.
- 1993
- IEDM 1993
High transconductance 0.1 μ m pMOSFET
- Y. Taur
- S. Cohen
- et al.
- 1992
- IEDM 1992