Optimizing stressor film deposition sequence in polish rate order for best planarization
- John H. Zhang
- Changyong Xiao
- et al.
- 2011
- MRS Spring Meeting 2011
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12 results for Haoren Zhuang
32nm general purpose bulk CMOS technology for high performance applications at low voltage
- F. Arnaud
- J. Liu
- et al.
- 2008
- IEDM 2008
Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices
- J.-P. Han
- H. Utomo
- et al.
- 2006
- IEDM 2006
65nm CMOS technology for low power applications
- A. Steegen
- R. Mo
- et al.
- 2005
- IEDM 2005
Single exposure contacts are dead. Long live single exposure contacts!
- Henning Haffner
- Martin Ostermayr
- et al.
- 2011
- SPIE Advanced Lithography 2011
Comparative study of CVD TiN vs. ALD TiN for contact metallization in 32nm node and beyond
- Valli Arunachalam
- Filippos Papadatos
- et al.
- 2010
- ADMETA 2010
High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
- D.-G. Park
- K. Stein
- et al.
- 2009
- VLSI-TSA 2009
Developing contact oxide CUP process for 32 nm technology nodes
- John H. Zhang
- Rajasekhar Venigalla
- et al.
- 2008
- VMIC 2008
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
- X. Chen
- S. Samavedam
- et al.
- 2008
- VLSI Technology 2008
32 NM Logic patterning options with immersion lithography
- K. Lai
- S. Burns
- et al.
- 2008
- SPIE Advanced Lithography 2008