Design and CAD Challenges in sub-90nm CMOS Technologies
- Kerry Bernstein
- Ching-Te Chuang
- et al.
- 2003
- ICCAD 2003
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22 results for K. Bernstein
Soft error rate scaling for emerging SOI technology options
- P. Oldiges
- K. Bernstein
- et al.
- 2002
- VLSI Technology 2002
Analysis of the effect of the gate oxide breakdown on SRAM stability
- R. Rodríguez
- J.H. Stathis
- et al.
- 2002
- Microelectronics Reliability
Device and architecture outlook for beyond CMOS switches
- Kerry Bernstein
- Ralph K. Cavin
- et al.
- 2010
- Proceedings of the IEEE
Mitigating memory wall effects in high-clock-rate and multicore CMOS 3-D processor memory stacks
- Philip Jacob
- Aamir Zia
- et al.
- 2009
- Proceedings of the IEEE
Thermomechanical modeling of 3D electronic packages
- Sri M. Sri-Jayantha
- Gerard McVicker
- et al.
- 2008
- IBM J. Res. Dev
Three-dimensional integrated circuits
- Anna W. Topol
- Douglas C. La Tulipe Jr.
- et al.
- 2006
- IBM J. Res. Dev
Ultralow-voltage minimum-energy CMOS
- Scott Hanson
- Bo Zhai
- et al.
- 2006
- IBM J. Res. Dev
High-performance CMOS variability in the 65-nm regime and beyond
- Kerry Bernstein
- David J. Frank
- et al.
- 2006
- IBM J. Res. Dev
Scaling planar silicon devices
- Ching-Te Chuang
- Kerry Bernstein
- et al.
- 2004
- IEEE Circuits and Devices Magazine