Impact of interconnect length changes on effective materials properties (dielectric constant)
- Mary Y. Lanzerotti
- Giovanni Fiorenza
- et al.
- 2007
- SLIP 2007
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12 results for G. Fiorenza
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry
- M.Y. Lanzerotti
- G. Fiorenza
- et al.
- 2005
- SLIP 2005
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution
- G.G. Lopez
- G. Fiorenza
- et al.
- 2005
- GLSVLSI 2005
Power optimization methodology for the IBM POWER7 microprocessor
- Victor V. Zyuban
- Joshua Friedrich
- et al.
- 2011
- IBM J. Res. Dev
Modeling of alpha-induced single event upsets for 45 nm node SOI devices using realistic C4 and 3D circuit geometries
- Henry H. K. Tang
- Conal E. Murray
- et al.
- 2009
- IEEE TNS
New simulation methodology for effects of radiation in semiconductor chip structures
- Henry H.K. Tang
- Conal E. Murray
- et al.
- 2008
- IBM J. Res. Dev
Importance of BEOL modeling in single event effect analysis
- Henry H. K. Tang
- Conal E. Murray
- et al.
- 2007
- IEEE TNS
Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements
- Mary Yvonne Lanzerotti
- Giovanni Fiorenza
- et al.
- 2005
- IBM J. Res. Dev
Interpretation of Rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models
- Mary Yvonne Lanzerotti
- Giovanni Fiorenza
- et al.
- 2004
- IEEE Transactions on VLSI Systems
Assessment of on-chip wire-length distribution models
- Mary Y. Lanzerotti
- Giovanni Fiorenza
- et al.
- 2004
- IEEE Transactions on VLSI Systems