Formation of nanometer-scale dot arrays from diblock copolymer templates
- C.T. Black
- K.W. Guarini
- et al.
- 2002
- Materials Research Society Symposium - Proceedings
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55 results for Y. Zhang
New polysilicon disposable sidewall process for sub-50 nm CMOS
- K.L. Lee
- D. Boyd
- et al.
- 2001
- ESSDERC 2001
Triple-self-aligned, planar double-gate MOSFETs: Devices and circuits
- K.W. Guarini
- P. Solomon
- et al.
- 2001
- Technical Digest-International Electron Devices Meeting
100 nm gate lithography for double gate transistors
- Azalia Krasnoperova
- Ying Zhang
- et al.
- 2001
- Proceedings of SPIE - The International Society for Optical Engineering
Very high performance 50 nm CMOS at low temperature
- S.J. Wind
- L.T. Shi
- et al.
- 1999
- IEDM 1999