R.D. Murphy, R.O. Watts
Journal of Low Temperature Physics
We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/ebeam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.
R.D. Murphy, R.O. Watts
Journal of Low Temperature Physics
J.R. Thompson, Yang Ren Sun, et al.
Physica A: Statistical Mechanics and its Applications
P.C. Pattnaik, D.M. Newns
Physical Review B
T.N. Morgan
Semiconductor Science and Technology