Methodology Development to Benchmark Power Delivery Designs in Advanced Technology Nodes
- Nicholas A. Lanzillo
- A. Chu
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
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84 results for Lawrence Clevenger
Subtractive Ru Interconnect Enabled by Novel Patterning Solution for EUV Double Patterning and TopVia with Embedded Airgap Integration for Post Cu Interconnect Scaling
- C. J. Penny
- Koichi Motoyama
- et al.
- 2022
- IEDM 2022
Benchmarking Power Delivery Network Designs at the 5-nm Technology Node
- Nicholas A. Lanzillo
- Albert M. Chu
- et al.
- 2021
- IEEE T-ED
Structural and transport properties of Cu/Ta(N)/Cu interfaces in vertical interconnects
- Nicholas A. Lanzillo
- Lawrence Clevenger
- et al.
- 2020
- Journal of Applied Physics
System Performance: From Enterprise to AI
- Arvind Kumar
- Leland Chang
- et al.
- 2018
- IEDM 2018
Strategy of Insertion of Merge Features in a Sea of Wires SADP Integration
- James H.-C. Chen
- Terry A. Spooner
- et al.
- 2018
- IITC 2018
Impact of Line and Via Resistance on Device Performance at the 5nm Gate All Around Node and beyond
- Nicholas A. Lanzillo
- Koichi Motoyama
- et al.
- 2018
- IITC 2018
Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
- Benjamin D. Briggs
- C.B. Pcethala
- et al.
- 2018
- IITC 2018
Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node
- Benjamin D. Briggs
- C.B. Peethala
- et al.
- 2017
- IEDM 2017
Layout based Monte-Carlo simulation (LBMCS) for complex back end of line (BEOL) design rule study
- Dongbing Shao
- Lawrence Clevenger
- et al.
- 2017
- IITC 2017