High Performance Nanosheet Technology Optimized for 77 K
- R. Bao
- L. Qin
- et al.
- 2023
- IEDM 2023
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16 results for S. Siddiqui
A comparative study of strain and Ge content in Si1-xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs
- Choonghyun Lee
- Shogo Mochizuki
- et al.
- 2017
- IEDM 2017
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Future on-chip interconnect metallization and electromigration
- C. K. Hu
- James Kelly
- et al.
- 2018
- IRPS 2018
Electromigration and resistivity in on-chip Cu, Co and Ru damascene nanowires
- C. K. Hu
- James Kelly
- et al.
- 2017
- IITC 2017
Selective GeOx-scavenging from interfacial layer on Si1-xGex channel for high mobility Si/Si1-xGex CMOS application
- Choonghyun Lee
- H. Kim
- et al.
- 2016
- VLSI Technology 2016
Experimental study of nanoscale Co damascene BEOL interconnect structures
- James Kelly
- James H.-C. Chen
- et al.
- 2016
- IITC/AMC 2016