Detection of Printable EUV Mask Absorber Defects and Defect Adders by Full Chip Optical Inspection of EUV Patterned WafersLuciana MeliRavi Bonamet al.2017IEEE Trans Semicond Manuf
Proposal of Package Structure Requirements for Effective Cooling from the Bottom Side of Chips (from the Substrate Side), Aiming for a Three-Dimensional (3D) Chip StackKeiji MatsumotoHiroyuki Mori2016ECTC 2016
Detection of printable EUV mask absorber defects and defect adders by full chip optical inspection of EUV patterned wafersLuciana MeliScott D. Halleet al.2016ASMC 2016
Essential edge protection techniques for successful multi-wafer stackingJoshua RubinKevin Winstelet al.2015S3S 2015
Warpage analysis of organic substrates for 2.1D packagingSayuri KoharaKeishi Okamotoet al.20153DIC 2015
Advances in percolated thermal underfill (PTU) simulations for 3D-integrationSridhar KumarUwe Zschenderleinet al.2015EuroSimE 2015