High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
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18 results at VLSI Technology 2005
HfO 2/metal stacks: Determination of energy level diagram, work functions & their dependence on metal deposition
- S. Zafar
- V. Narayanan
- et al.
- 2005
- VLSI Technology 2005
Stable SRAM cell design for the 32 nm node and beyond
- Leland Chang
- David M. Fried
- et al.
- 2005
- VLSI Technology 2005
High performance FDSOI CMOS technology with metal gate and high-k
- Bruce Doris
- Y.-H. Kim
- et al.
- 2005
- VLSI Technology 2005
Role of oxygen vacancies in VFB/Vt stability of pFET metals on HfO2
- E. Cartier
- F.R. McFeely
- et al.
- 2005
- VLSI Technology 2005
Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates
- Qiqing Ouyang
- Min Yang
- et al.
- 2005
- VLSI Technology 2005
Mobility and CMOS devices/circuits on sub-10nm (110) ultra thin body SOI
- Huiling Shang
- J. Rubino
- et al.
- 2005
- VLSI Technology 2005
Dual stress liner enhancement in hybrid orientation technology
- C. Sheraw
- M. Yang
- et al.
- 2005
- VLSI Technology 2005
Extremely-scaled double-gate CMOS with non-self-aligned back gate
- Keunwoo Kim
- Hussein I. Hanafi
- et al.
- 2005
- VLSI Technology 2005
High mobility solution-deposited chalcogenide films for flexible applications
- David B. Mitzi
- Delia J. Milliron
- et al.
- 2005
- VLSI Technology 2005