Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect densityMilos StanisavljevicFrank Kagan Gürkaynaket al.2007GLSVLSI 2007
Structured and tuned array generation (STAG) for high-performance random logicMatthew M. ZieglerGary S. Ditlowet al.2007GLSVLSI 2007