Architecture and Design Approaches towards Large-scale AI Hardware Acceleration
- Ashish Ranjan
- 2025
- DAC 2025
Publications
242 results for AI Hardware
Routing Congestion Mitigation Techniques Targeting Dense Designs
- Alex Suess
- Lakshmi Reddy
- et al.
- 2025
- DAC 2025
DiReC: Enhancing VHDL Code Generation and Summarization with Divide-Retrieve-Conquer Strategy
- Prashanth Vijayaraghavan
- Apoorva Nitsure
- et al.
- 2025
- DAC 2025
On-Chip Training and Inference using Analog CMO/HfOx ReRAM Artificial Synapses
- Donato Francesco Falcone
- Victoria Clerico
- et al.
- 2025
- Neuronics 2025
Deep Neural Network Inference with Analog In-Memory Computing
- 2025
- PASC 2025
A 6+ GHz 128KB Multi-Port L1 Cache using Ground Rule Clean 10T Bitcells in 5nm Technology
- Rajiv Joshi
- John Davis
- et al.
- 2025
- VLSI Technology and Circuits 2025
Heterogeneous neural processing units leveraging analog in-memory computing for edge AI
- 2025
- VLSI Technology and Circuits 2025
Tile Efficiency is not System Efficiency – CIM architecture studies of LLMs and other large DNNs
- Pritish Narayanan
- 2025
- VLSI Technology and Circuits 2025
Chiplet and Heterogeneous integration Technologies for HPC and AI
- 2025
- VLSI Technology and Circuits 2025
Architectural Benchmarking of Compute-in-Memory Systems
- Pritish Narayanan
- Sidney Tsai
- 2025
- VLSI Technology and Circuits 2025
