Huiming Bu

Title

Vice President: IBM Semiconductors Global R&D and Albany Operations

Bio

Dr. Huiming Bu is responsible for IBM global Semiconductor R&D strategy across world-wide labs. He oversees R&D activities in advanced logic, chiplet and advanced packaging, emerging memory and analog AI hardware at IBM Research. In addition to leading semiconductor technology R&D agenda, Huiming is also responsible for IBM Research Albany Lab site and fab operations.

Huiming has ~20 years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. Huiming has authored/co-authored 100+ technical publications and holds 100+ patents in semiconductor domain.

Huiming started his technical career at IBM on High-κ/Metal Gate project and then led SOI FinFET research and early development for IBM’s 14nm node technology. After that, Huiming and his team delivered 10nm/7nm technology R&D for IBM and its Joint Development Alliance (JDA) partners. They are now working on 2nm development and 1nm & beyond pathfinding R&D. Recently, as IBM formed Semiconductors division under IBM Research, the footprint has expanded from advanced logic to chiplet & advanced packaging, intelligent fab, cloud based EDA and design.

Publications

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond
- - Q. Liu
  - M. Vinet
  - et al.
- 2013
- IEDM 2013
Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs
- - Abhijeet Paul
  - Chun-Chen Yeh
  - et al.
- 2013
- S3S 2013
Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs
- - A. Khakifirooz
  - R. Sreenivasan
  - et al.
- 2013
- S3S 2013
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- - S. Lee
  - Richard A. Wachnik
  - et al.
- 2013
- VLSI Technology 2013
Channel doping impact on FinFETs for 22nm and beyond
- - Chung-Hsun Lin
  - R. Kambhampati
  - et al.
- 2012
- VLSI Technology 2012
Physical characterization of sub-32-nm semiconductor materials and processes using advanced ion beam-based analytical techniques
- - M. Hopstaken
  - D. Pfeiffer
  - et al.
- 2012
- Surface and Interface Analysis
Analysis of parasitic resistance in double gate FinFETs with different fin lengths
- - X. Yang
  - Kingsuk Maitra
  - et al.
- 2011
- IEEE International SOI Conference 2011
FINFET technology a substrate perspective
- - Huiming Bu
- 2011
- IEEE International SOI Conference 2011
Assessment of fully-depleted planar CMOS for low power complex circuit operation
- - Zhibin Ren
  - S. Mehta
  - et al.
- 2011
- IEDM 2011
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- - S. Krishnan
  - U. Kwon
  - et al.
- 2011
- IEDM 2011

Patents

- 09 Dec 2024
- US
- 12166042
Stacked Nanosheet Gate-all-around Device Structures
- 31 Oct 2023
- TW
- I821132
Self-aligned Backside Contact With Increased Contact Area
- 09 May 2022
- US
- 11329136
Enabling Anneal For Reliability Improvement And Multi-vt With Interfacial Layer Regrowth Suppression
- 04 Oct 2021
- US
- 11139385
Interface-less Contacts To Source/drain Regions And Gate Electrode Over Active Portion Of Device
- 09 Aug 2021
- US
- 11088278
Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers
- 17 May 2021
- US
- 11011513
Integrating A Junction Field Effect Transistor Into A Vertical Field Effect Transistor
- 01 Mar 2021
- US
- 10937867
Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices
- 11 Jan 2021
- US
- 10892181
Semiconductor Device With Mitigated Local Layout Effects
- 19 Oct 2020
- US
- 10811528
Two Step Fin Etch And Reveal For Vtfets And High Breakdown Ldvtfets
- 17 Aug 2020
- US
- 10748893
Electrostatic Discharge Devices And Methods Of Manufacture

Top collaborators

Huiming Bu

Title

Bio

Publications

High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond

Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs

Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs

Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices

Channel doping impact on FinFETs for 22nm and beyond

Physical characterization of sub-32-nm semiconductor materials and processes using advanced ion beam-based analytical techniques

Analysis of parasitic resistance in double gate FinFETs with different fin lengths

FINFET technology a substrate perspective

Assessment of fully-depleted planar CMOS for low power complex circuit operation

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Patents

Stacked Nanosheet Gate-all-around Device Structures

Self-aligned Backside Contact With Increased Contact Area

Enabling Anneal For Reliability Improvement And Multi-vt With Interfacial Layer Regrowth Suppression

Interface-less Contacts To Source/drain Regions And Gate Electrode Over Active Portion Of Device

Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers

Integrating A Junction Field Effect Transistor Into A Vertical Field Effect Transistor

Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices

Semiconductor Device With Mitigated Local Layout Effects

Two Step Fin Etch And Reveal For Vtfets And High Breakdown Ldvtfets

Electrostatic Discharge Devices And Methods Of Manufacture

Top collaborators

Dechao Guo

Dan J. Dechene

Hemanth Jagannathan

Nick Lanzillo