Matthias Brändli

Title

Digital Circuit Design

Publications

A 24-72-GS/s 8-b time-interleaved SAR ADC with 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- IEEE JSSC
A 12-bit 300-MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14-nm CMOS FinFET
- - Danny Luu
  - Lukas Kull
  - et al.
- 2018
- IEEE JSSC
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
- - Thomas Toifl
  - Christian Menolfi
  - et al.
- 2018
- VLSI Circuits 2018
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
- - Pier Andrea Francese
  - Alessandro Cevrero
  - et al.
- 2018
- VLSI Circuits 2018
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- VLSI Circuits 2018
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders
- - Hazar Yueksel
  - Matthias Braendli
  - et al.
- 2018
- IEEE TCAS-I
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver
- - Gain Kim
  - Lukas Kull
  - et al.
- 2018
- ISCAS 2018
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver with Low-Latency Digital CDR in 14-nm CMOS FinFET
- - Ilter Ozkaya
  - Alessandro Cevrero
  - et al.
- 2018
- IEEE JSSC
A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- ISSCC 2018
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
- - Christian Menoifi
  - Matthias Braendli
  - et al.
- 2018
- ISSCC 2018

Patents

- 16 Sep 2024
- US
- 12095473
Time Domain Interleaving
- 13 Nov 2023
- US
- 11816062
Control Unit For Qubits
- 05 Jul 2021
- US
- 11057039
Clock Divider With Quadrature Error Correction
- 14 Nov 2016
- US
- 9496008
Determination Of A Common Mode Voltage

Projects

High-Speed I/O Links

Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.

View more projects

Top collaborators

Thomas Morf

Senior Research Scientist

Pier Andrea Francese

Principal RSM - Analog Circuit Design

Marcel Kossel

Circuit Designer

Cezar Zota

Staff Research Scientist, Master inventor