Matthias Brändli

Title

Digital Circuit Design

Publications

A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS
- - Ilter Ozkaya
  - Alessandro Cevrero
  - et al.
- 2018
- ISSCC 2018
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels
- - Cosimo Aprile
  - Alessandro Cevrero
  - et al.
- 2018
- IEEE JSSC
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
- - Ilter Ozkaya
  - Alessandro Cevrero
  - et al.
- 2017
- IEEE JSSC
DDR4 transmitter with ac-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS Technology
- - Marcel Kossel
  - Christian Menolfi
  - et al.
- 2017
- ESSCIRC 2017
Background calibration using noisy reference ADC for a 12b 600MS/s 2×TI SAR ADC in 14nm CMOS FinFET
- - Danny Luu
  - Lukas Kull
  - et al.
- 2017
- ESSCIRC 2017
A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2017
- VLSI Circuits 2017
A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V
- - Elisa Sacco
  - Pier Andrea Francese
  - et al.
- 2017
- VLSI Circuits 2017
A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET
- - Danny Luu
  - Lukas Kull
  - et al.
- 2017
- VLSI Circuits 2017
A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET
- - Lukas Kull
  - Danny Luu
  - et al.
- 2017
- ISSCC 2017
A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET
- - Alessandro Cevrero
  - Ilter Ozkaya
  - et al.
- 2017
- ISSCC 2017

Patents

- 16 Sep 2024
- US
- 12095473
Time Domain Interleaving
- 13 Nov 2023
- US
- 11816062
Control Unit For Qubits
- 05 Jul 2021
- US
- 11057039
Clock Divider With Quadrature Error Correction
- 14 Nov 2016
- US
- 9496008
Determination Of A Common Mode Voltage

Projects

High-Speed I/O Links

Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.

View more projects

Top collaborators

Thomas Morf

Senior Research Scientist

Pier Andrea Francese

Principal RSM - Analog Circuit Design

Marcel Kossel

Circuit Designer

Cezar Zota

Staff Research Scientist, Master inventor