Shaoning Yao, Wei-Tsu Tseng, et al.
ADMETA 2011
As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layerspecific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1 μm2 and other critical features across the chip with a process window are demonstrated. © 2010 Society of Photo-Optical Instrumentation Engineers.
Shaoning Yao, Wei-Tsu Tseng, et al.
ADMETA 2011
Sharee J. McNab, Richard J. Blaikie
Materials Research Society Symposium - Proceedings
Kenneth R. Carter, Robert D. Miller, et al.
Macromolecules
Elizabeth A. Sholler, Frederick M. Meyer, et al.
SPIE AeroSense 1997