Woogeun Rhee, Biagio Bisanti, et al.
IEEE Journal of Solid-State Circuits
A 10-Gb/s clock and data recovery (CDR) circuit and a 1:4 DMUX are implemented in 0.12-μm CMOS. The CDR employs a secondary wideband delay-locked loop (DLL) to enable independent bandwidth control for jitter transfer and jitter tolerance. The proposed clock recovery and data recovery (CRDR) system enhances the jitter tolerance at high frequencies and offers less data-pattern-dependency for CDRs that use a binary phase detector.
Woogeun Rhee, Biagio Bisanti, et al.
IEEE Journal of Solid-State Circuits
Troy Beukema, Michael Sorna, et al.
IEEE Journal of Solid-State Circuits
Mark Ferriss, Alexander Rylyakov, et al.
VLSI Circuits 2013
Sergey Rylov, Alexander Rylyakov
BCTM 2003