Clint Schow, Fuad Doany, et al.
ISSCC 2008
A 6b 10 tap-full rate distributed arithmetic digital finite impulse response filter (DFIR) is reported using dynamic logic datapath with independent precharge and compute signals per domino stage. The basic architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. Two 8b 16-entry loadable tables contain the precomputed partial sums used by the distributed arithmetic algorithms.
Clint Schow, Fuad Doany, et al.
ISSCC 2008
Solomon Assefa, Steven Shank, et al.
OECC/PS 2013
Lei Shan, Mounir Meghelli, et al.
ECTC 2003
Jose Tierno, Alexander Rylyakov, et al.
ISSCC 2002