Lukas Kull, Danny Luu, et al.
ISSCC 2017
A 12.5Gb/s receiver circuit with 8-tap decision feedback equalizer (DFE) is presented, which consumes only 2.6mW/Gb/s, and was measured to receive data error-free over a channel with -27dB attenuation. The receiver uses a switched-capacitor (SC) approach for the DFE, where charge is added to the summation node by switching digitally adjustable capacitances dependent on the received data history. © 2011 JSAP (Japan Society of Applied Physi.
Lukas Kull, Danny Luu, et al.
ISSCC 2017
Jonathan E. Proesel, Timothy O. Dickson
VLSI Circuits 2011
Alessandro Cevrero, Ilter Ozkaya, et al.
ISSCC 2019
Thomas Toifl, Christian Menolfi, et al.
IEEE Journal of Solid-State Circuits