A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS
- Thomas Toifl
- Michael Ruegg
- et al.
- 2012
- VLSI Circuits 2012
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7 results for Michael Ruegg
A 2.6mW/Gbps 12.5Gbps RX with 8-tap switched-cap DFE in 32nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2011
- VLSI Circuits 2011
A 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technology
- Thomas Toifl
- Christian Menolfi
- et al.
- 2005
- VLSI Circuits 2005
A 2.6 mW/Gbps 12.5 Gbps RX with 8-Tap switched-capacitor DFE in 32 nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS
- Robert Reutemann
- Michael Ruegg
- et al.
- 2010
- IEEE Journal of Solid-State Circuits
A 22-Gb/s PAM-4 receiver in 90-nm CMOS SOI technology
- Thomas Toifl
- Christian Menolfi
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
A 0.94-ps-RMS-Jitter 0.016-mm 2 2.5-GHz Multiphase Generator PLL with 360° Digitally Programmable Phase Shift for 10-Gb/s Serial Links
- Thomas Toifl
- Christian Menolfi
- et al.
- 2005
- IEEE Journal of Solid-State Circuits