Daniel M. Kuchta, Jonathan E. Proesel, et al.
OFC 2019
This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level package, connecting high-speed optical I/O directly to an advanced CMOS host chip (e.g., processor and switch) to increase package I/O bandwidth density and lower overall system power and cost. The optical link is designed for maximum link margin to tolerate high optical losses created by low-cost optical packaging. The transmitter (TX) uses a three-tap, 1/2-unit-interval-spaced feed-forward equalizer to improve eye opening. The receiver (RX) uses a low-bandwidth, low-noise transimpedance amplifier and a speculative one-tap decision-feedback equalizer for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4 pJ/bit, respectively. The TX optical modulation amplitude (OMA) is 1.2 dBm, and the RX sensitivity is-11.7 dBm OMA at a bit error rate of 10-12 with PRBS31 data, providing 12.9-dB link margin.
Daniel M. Kuchta, Jonathan E. Proesel, et al.
OFC 2019
Jonathan E. Proesel, Clint L. Schow, et al.
OFC 2012
Alexander V. Rylyakov, Jonathan E. Proesel, et al.
IEEE JSSC
Jonathan E. Proesel, Zeynep Toprak-Deniz, et al.
VLSI Circuits 2017