A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces

This paper describes a 64K CMOS RAM with ECL interfaces having access times of 6.2 ns at room temperature and, with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature. The CMOS processes feature a 0.5-μm L, self-aligned TiSi, double-level metal, and an average minimum feature size of 1.35 μm. Circuits key to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation are discussed including circuit/device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits. © 1989 IEEE