Swagath Venkataramani, Jungwook Choi, et al.
IEEE Micro
A 32kb subarray demonstrates practiedl implementation of a 65nm node 8T-SRAM cell for variability tolerance in highspeed caches. Ideal cell stability allows single-supply operation down to 0.41V at 295MHz without dynamic voltage techniques. Despite a larger cell, array area is competitive with 6T-SRAM due to higher array efficiency. With an LSDL decoder, a gated diode sense amplifier, and design tradeoffs enabled by the 8T cell, 5.3GHz operation at 1.2 V is achieved.
Swagath Venkataramani, Jungwook Choi, et al.
IEEE Micro
Suyoung Bang, Jae-Sun Seo, et al.
IEEE JSSC
Dheeraj Sreedhar, J.H. Derby, et al.
HiPC 2014
Juan Antonio Carballo, David L. Cohn, et al.
SPIE Advanced Microelectronic Manufacturing 2003