Power and performance optimization at the system level
Valentina Salapura, Randy Bickford, et al.
CF 2005
Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix [2], [20] and its inverse [3], [9], 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods [29]. Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach used in [8] and [28]. It then extends the extraction algorithm in [29] to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.
Valentina Salapura, Randy Bickford, et al.
CF 2005
Alina Deutsch, Gerard V. Kopcsay, et al.
IEEE Transactions on Advanced Packaging
Mark E. Giampapa, Ralph Bellofatto, et al.
IBM J. Res. Dev
Alina Deutsch, Gerard V. Kopcsay, et al.
IEEE Trans Electromagn Compat