TDDB Reliability in Gate-All-Around Nanosheet
Huimei Zhou, Miaomiao Wang, et al.
IRPS 2021
Ultra-fast (Iuus delay) measured threshold voltage shift (ΔVT) due to Negative Bias Temperature Instability (NBTI) in Gate All Around Stacked Nano-Sheet (GAA-SNS) Field Effect Transistors (FETs) having various length (L) and width (W) are analyzed. An enhanced, fully physical BTI Analysis Tool (BAT) is used to model the measured ΔVT stress-recovery kinetics at multiple stress bias (VGSTR) and temperature (T), with only four process dependent parameters. The impact of L and W scaling on ΔVT magnitude and its Voltage Acceleration Factor (VAF) is explained by considering variation in mechanical stress.
Huimei Zhou, Miaomiao Wang, et al.
IRPS 2021
Robert L. Bruce, Syed Ghazi Sarwat, et al.
IRPS 2021
Paul Solomon, Douglas M. Bishop, et al.
IRPS 2021
Gokul Krishnan, Jingbo Sun, et al.
IRPS 2021