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A New Clustering-Function-Based Formulation of Temporal and Spatial Clustering Model Involving Area Scaling and its Application to Parameter ExtractionErnest WuBrian McGowanet al.2024IRPS 2024
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet TechnologyShogo MochizukiNicolas Loubetet al.2023IEDM 2023
Impact of Gate Stack Thermal Budget on NBTI Reliability in Gate-All-Around Nanosheet P-type DevicesHuimei ZhouMiaomiao Wanget al.2023IRPS 2023
Gate-Last IO Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic TechnologiesM. BhuiyanM. Kimet al.2021IEDM 2021
Critical Elements for Next Generation High Performance Computing Nanosheet TechnologyR. BaoC. Durfeeet al.2021IEDM 2021
Challenges and Opportunities for Stacked Transistor: DTCO and DeviceJ. WangS.D. Suket al.2021VLSI Technology 2021
Analysis of Sheet Dimension (W, L) Dependence of NBTI in GAA-SNS FETsNilotpal ChoudhuryTarun Samadderet al.2021IRPS 2021