Leakage aware Si/SiGe CMOS FinFET for low power applications
G. Tsutsui, C. Durfee, et al.
VLSI Technology 2018
Cu grain size analysis, electrical measurements, and electromigration reliability tests were carried out in 50 nm wide features to evaluate low temperature reflow anneals of physical vapor deposited Cu as an alternative metallization scheme for BEOL Cu/low-k integration. Comparable final Cu grain size is observed between control electroplated samples and reflow annealed samples, and observed line resistance reduction from the reflow annealed samples is attributed to higher purity within the Cu interconnects. Both electrical measurements and electromigration test results confirm feasibility of this reflow anneal approach for BEOL Cu integration. © 2013 The Electrochemical Society.
G. Tsutsui, C. Durfee, et al.
VLSI Technology 2018
Joyeeta Nag, Brian A. Cohen, et al.
ECS Meeting 2015 Phoenix
Ramachandran Muralidhar, Ernest Y. Wu, et al.
IRPS 2017
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