Surendra B. Anantharaman, Joachim Kohlbrecher, et al.
MRS Fall Meeting 2020
CNFETs were fabricated in a top gate construction. The thin dielectric offered improved electrical performance relative to substrate-gated CNFETs with thicker gate dielectrics, at a fraction of the gate voltage. The top gate structure also offered individual switchability, as well as stable n-FET and p-FET devices, enabling the possibility of future CMOS CNFET circuits.
Surendra B. Anantharaman, Joachim Kohlbrecher, et al.
MRS Fall Meeting 2020
Arvind Kumar, Jeffrey J. Welser, et al.
MRS Spring 2000
T.N. Morgan
Semiconductor Science and Technology
Shu-Jen Han, Dharmendar Reddy, et al.
ACS Nano