Electromigration characteristics of power grid like structures
Baozhen Li, Andrew Kim, et al.
IRPS 2018
Hard breakdown is shown to be a gradual process with the gate current increasing at a predictable rate, exponentially dependent on the instantaneous stress voltage. Adding the hard breakdown evolution time to the standard time to breakdown potentially reduces the projected fail rate of gate dielectrics by orders of magnitude. The scaling of the hard breakdown growth rate with respect to device area, substrate doping, oxide thickness, and channel length are. explored. A two-voltage stress procedure is introduced that measures degradation rates on sub-micron devices several orders of magnitude more quickly than a conventional single voltage stress.
Baozhen Li, Andrew Kim, et al.
IRPS 2018
Miaomiao Wang, Sufi Zafar, et al.
Microelectronic Engineering
Narendra Parihar, Richard G. Southwick, et al.
IEEE T-ED
Jae-Joon Kim, Barry P. Linder, et al.
IRPS 2011