Conference paperA 34&181;m2DRAM cell fabricated with a 1&181;m single-level polycide FET technologyHu H. Chao, Robert H. Dermard, et al.ISSCC 1981
PaperA Fully Scaled Submicrometer NMOS Technology Using Direct-Write E-Beam LithographyMatthew R. Wordeman, April M. Schweighart, et al.IEEE T-ED
PaperFlexible test mode approach for 256-Mb DRAMToshiaki Kirihata, Hing Wong, et al.IEEE Journal of Solid-State Circuits
Paper1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macroOsamu Takahashi, Sang H. Dhong, et al.IEEE Journal of Solid-State Circuits
