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EOS/ESD 2000
This paper is a review of the latchup phenomena in past and present CMOS technologies. Both static and transient characterization techniques are described, as well as process related solutions and layout groundrule constraints. Technology scaling implications are discussed in the context of latchup holding voltage/current and minimum N+ to P+ spacing.
S. Voldman, P. Juliano, et al.
EOS/ESD 2000
M. Hargrove, S.W. Crowder, et al.
IEDM 1998
K. Chatty, P.E. Cottrell, et al.
IRPS 2004
P. Smeys, V. McGahay, et al.
VLSI Technology 2000