Thomas M. Cover
IEEE Trans. Inf. Theory
As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.
Thomas M. Cover
IEEE Trans. Inf. Theory
Ruixiong Tian, Zhe Xiang, et al.
Qinghua Daxue Xuebao/Journal of Tsinghua University
Fan Zhang, Junwei Cao, et al.
IEEE TETC
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000