Material and device integration for hybrid III-V/SiGe CMOS technology

A dense co-integration of nano-scaled InGaAs n-FETs and SiGe p-FETs is envisaged for future low power and high performance CMOS in sub-10 nm regime. It is, therefore, essential to have a scalable material and device integration scheme for such a hybrid CMOS. In this paper we report InGaAs integration methods on large scale Si substrates through wafer bonding or selective epitaxy. We then show high performance InGaAs-OI device integration routes. Based on these integration schemes, we further discuss strategies for scaled InGaAs/SiGe hybrid CMOS in 2D and 3D integration platforms.