New polysilicon disposable sidewall process for sub-50 nm CMOS
K.L. Lee, D. Boyd, et al.
ESSDERC 2001
Quantum-mechanical modeling of electron tunneling current from the quantized inversion layer of ultra-thin-oxide (<40 Å) nMOSFET's is presented, together with experimental verification. An accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitance-versus-voltage curves to quantum-mechanically simulated capacitance-versus-voltage results. The lifetimes of quasibound states and the direct tunneling current are calculated using a transverse-resonant method. These results are used to project an oxide scaling limit of 20 Å before the chip standby power becomes excessive due to tunneling currents.
K.L. Lee, D. Boyd, et al.
ESSDERC 2001
D.A. Buchanan, A.D. Marwick, et al.
Journal of Applied Physics
Y. Taur, Y. Mii, et al.
IBM J. Res. Dev
Eric D. Johnson, T.B. Hook, et al.
VLSI Technology 1990