PaperOxide scaling limit for future logic and memory technologyJ.H. Stathis, D.J. DiMariaMicroelectronic Engineering
PaperWorn-out oxide MOSFET characteristics: Role of gate current and device parameters on a current mirrorJ. Martín-Martínez, R. Rodríguez, et al.Microelectronics Reliability
Conference paperPhysical and predictive models of ultra thin oxide reliability in CMOS devices and circuitsJ.H. StathisIRPS 2001
Conference paperPBTI relaxation dynamics after ac VS. DC stress in high-K/metal gate stacksK. Zhao, J.H. Stathis, et al.IRPS 2010