Ruqiang Bao, K. Watanabe, et al.
VLSI Technology 2020
A fast two-point measurement methodology, applicable to nano-scale devices, is introduced to separate electron trapping (Not, e) from interface state contributions (Nit) in hot carrier (HC) induced ΔVt in n-type RMG SOI FinFETs. It is shown that Not, e component is comparable to or dominates over Nit for high-Vg (≥ Vd) hot carrier stress (HCS). The time power-law exponent for HC induced Not, e is larger than 0.2, indicating the observed Not, e is partly due to injection of hot carriers instead of purely parasitic PBTI effect caused by the cold carriers.
Ruqiang Bao, K. Watanabe, et al.
VLSI Technology 2020
Veeraraghvan S. Basker, Theodorus E. Standaert, et al.
VLSI Technology 2010
Abhijeet Paul, Andres Bryant, et al.
IEDM 2013
Miaomiao Wang, Sufi Zafar, et al.
Microelectronic Engineering