REACTIVE ION ETCHING OF MULTI-LAYER RESIST.
- H.Y. Ng
- D.P. Klaus
- et al.
- 1986
- MRS Fall Meeting 1986
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32 results for H.Y. Ng
Inverter Performance Of Deep-Submicrometer Mosfet'S
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1988
- IEEE Electron Device Letters
Design and Experimental Technology for 0.1-μm Gate-Length Low-Temperature Operation FET's
- George A. Sai-Halasz
- Matthew R. Wordeman
- et al.
- 1987
- IEEE Electron Device Letters
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- S. Fang
- S.S. Tan
- et al.
- 2008
- ICSICT 2008
Channel Strain Characterization in Embedded SiGe by Nano-beam Diffraction
- J. Li
- A. Lamberti
- et al.
- 2008
- ECS Meeting 2008
Scalability of Direct Silicon Bonded (DSB) technology for 32nm node and beyond
- Haizhou Yin
- C.Y. Sung
- et al.
- 2007
- VLSI Technology 2007
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technology
- Z. Luo
- N. Rovedo
- et al.
- 2007
- VLSI Technology 2007
Patterning strategies for gate level tip-tip distance reduction in SRAM cell for 45nm and beyond
- Haoren Zhuang
- Helen Wang
- et al.
- 2007
- ISTC 2007
A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006