Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- H.S. Yang
- R. Malik
- et al.
- 2004
- IEDM 2004
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21 results for S. Subbanna
A High-Density 6.9 sq. pm Embedded SRAM Cell in a High-Performance 0.25 μm-Generation CMOS Logic Technology
- S. Subbanna
- P. Agnello
- et al.
- 1996
- IEDM 1996
Optimization of SiGe HBT Technology for High Speed Analog and Mixed-Signal Applications
- D.L. Harame
- J.M.C. Stork
- et al.
- 1993
- IEDM 1993
A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic
- S. Subbanna
- D.L. Harame
- et al.
- 1993
- IEDM 1993
3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay
- Basanth Jagannathan
- Mounir Meghelli
- et al.
- 2003
- IEEE Electron Device Letters
A 4.2-ps ECL ring-oscillator in a 285-GHz f MAX SiGe technology
- Basanth Jagannathan
- Mounir Meghelli
- et al.
- 2002
- IEEE Electron Device Letters
Self-aligned SiGe NPN transistors with 285 GHz f MAX and 207 GHz f T in a manufacturable technology
- B. Jagannathan
- M. Khater
- et al.
- 2002
- IEEE Electron Device Letters
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
High-performance silicon-germanium technology
- Seshadri Subbanna
- Greg Freeman
- et al.
- 2005
- DRC 2005
A comprehensive simulation study of strained-Si/SiGe nMODFET scaling for RF applications
- Qiqing Christine Ouyang
- S.J. Koester
- et al.
- 2002
- SISPAD 2002