Controlling floating-body effects for 0.13μm and 0.10μm SOI CMOS
- S.K.H. Fung
- N. Zamdmer
- et al.
- 2000
- IEDM 2000
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31 results for F. Assaderaghi
Sub-60 nm physical gate length SOI CMOS
- I.Y. Yang
- K. Chen
- et al.
- 1999
- IEDM 1999
High performance 0.18 μm SOI CMOS technology
- E. Leobandung
- E. Barth
- et al.
- 1999
- IEDM 1999
Scalability of SOI technology into 0.13 μm 1.2 V CMOS generation
- E. Leobandung
- M. Sherony
- et al.
- 1998
- IEDM 1998
7.9/5.5 psec room/low temperature SOI CMOS
- F. Assaderaghi
- W. Rausch
- et al.
- 1997
- IEDM 1997
0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
- D. Schepis
- F. Assaderaghi
- et al.
- 1997
- IEDM 1997
Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1996
- IEDM 1996
High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz fT
- Clement Wann
- Fariborz Assaderaghi
- et al.
- 1997
- IEEE Electron Device Letters
Transient pass-transistor leakage current in SOI MOSFET's
- F. Assaderaghi
- G. Shahidi
- et al.
- 1997
- IEEE Electron Device Letters
Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
- R.V. Joshi
- C.T. Chuang
- et al.
- 2001
- VLSI Technology 2001