Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Publications
Date
Featured collections
Popular topics
20 results for Albert Young
Accurate performance evaluation for the horizontal nanosheet standard-cell design space beyond 7nm technology
- Yoo-Mi Lee
- Myung-Hee Na
- et al.
- 2017
- IEDM 2017
A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding
- F. Liu
- R.R. Yu
- et al.
- 2008
- IEDM 2008
Interconnects in the third dimension: Design challenges for 3D ICs
- Kerry Bernstein
- Paul Andry
- et al.
- 2007
- DAC 2007
Structure, design and process control for Cu bonded interconnects in 3D integrated circuits
- Kuan-Neng Chen
- Sang Hwui Lee
- et al.
- 2006
- IEDM 2006
Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs)
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- IEDM 2005
Programmable via using indirectly heated phase-change switch for reconfigurable logic applications
- Ku N. Chen
- L. Krusin-Elbaum
- et al.
- 2008
- IEEE Electron Device Letters
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Rapid and Holistic Technology Evaluation for Exploratory DTCO in beyond 7nm Technologies
- Myung-Hee Na
- Albert Chu
- et al.
- 2018
- SISPAD 2018