Characterization of stacked die using die-to-wafer integration for high yield and throughput
- K. Sakuma
- P. Andry
- et al.
- 2008
- ECTC 2008
Publications
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44 results for Bucknell Webb
3D chip stacking technology with low-volume lead-free interconnections
- K. Sakuma
- P. Andry
- et al.
- 2007
- ECTC 2007
Assembly, characterization, and reworkability of Pb-free ultra-fine pitch C4s for system-on-package
- B. Dang
- S.L. Wright
- et al.
- 2007
- ECTC 2007
CMOS-compatible through silicon vias for 3D process integration
- Cornelia K. Tsang
- Paul S. Andry
- et al.
- 2006
- MRS Fall Meeting 2006
System-on-Package (SOP) technology, characterization and applications
- J. Knickerbocker
- P. Andry
- et al.
- 2006
- ECTC 2006
A CMOS-compatible process for fabricating electrical through-vias in silicon
- P. Andry
- C. Tsang
- et al.
- 2006
- ECTC 2006
A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer
- Noah Sturcken
- Eugene J. O'Sullivan
- et al.
- 2013
- IEEE JSSC
Packaging Issues and Solutions for Ultra-Low Power, High Efficiency GaN micro-LEDs for a Battery Free, Sub-mm2, Tetherless, Smart IoT System
- Frank R. Libsch
- S.W. Bedell
- et al.
- 2020
- IMAPS 2020
Flexible Piezoresistive Sensors Fabricated by Spalling Technique
- Katsuyuki Sakuma
- Huan Hu
- et al.
- 2018
- IFETC 2018
TSV/FET proximity study using dense addressable transistor arrays
- Raphael P. Robertazzi
- Kanak Agarwal
- et al.
- 2015
- IRPS 2015