Findings and considerations for I/O clock jitter on a source synchronous front side bus
- Daniel Dreps
- Len Daniels
- et al.
- 2012
- EPEPS 2012
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23 results for Daniel Dreps
Design methodology of high performance on-chip global interconnect using terminated transmission-line
- Yulei Zhang
- Ling Zhang
- et al.
- 2009
- ISQED 2009
On-chip bus signaling using passive compensation
- Yulei Zhang
- Ling Zhang
- et al.
- 2008
- EPEPS 2008
Low power passive equalizer design for computer memory links
- Ling Zhang
- Wenjian Yu
- et al.
- 2008
- HOTI 2008
How detrimental could a via be?
- Lei Shan
- Young Kwark
- et al.
- 2004
- IEEE Topical Meeting EPEPS 2004
Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
- S. Voldman
- D. Hui
- et al.
- 2000
- EOS/ESD 2000
IBM POWER8 circuit design and energy optimization
- Victor Zyuban
- Joshua Friedrich
- et al.
- 2015
- IBM J. Res. Dev
A 2.6 mW/Gbps 12.5 Gbps RX with 8-Tap switched-capacitor DFE in 32 nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
Analysis and optimization of low-power passive equalizers for cpu-memory links
- Ling Zhang
- Wenjian Yu
- et al.
- 2011
- IEEE Transactions on CPMT
IBM POWER7 processor circuit design
- Dieter Wendel
- John Barth
- et al.
- 2011
- IBM J. Res. Dev