On-chip bus signaling using passive compensation

A new scheme for bus signaling using on-chip lossy transmission lines with passive compensation is introduced in this paper to address the performance limitation brought by the scaling issues of on-chip global wires. The new scheme is designed and optimized based on eye-diagram prediction algorithm and sequential quadratic programming (SQP) flow. We perform a case study to demonstrate feasibility of the proposed scheme. The results show that, at 45nm technology node, the new scheme achieves 20.58ps/mm transmission speed and has the power efficiency of 0.106pJ/bit considering the crosstalk effects. © 2008 IEEE.